This invention generally relates to semiconductor devices and more specifically to SRAM cell designs.
A schematic of a typical static random access memory (SRAM) cell is shown in FIG. 1A. SRAM cells typically comprise a pair of cross-coupled inverters (12, 14) to store a data bit state and a pair of pass transistors (16, 18) to read and write a data bit between the cross-coupled inverters (12, 14) and bitlines (30, 32). Each inverter (12, 14) comprises a p-channel pull-up transistor (20, 22) and a n-channel pull-down transistor (24, 26). This type of SRAM cell comprises 6 transistors and is termed a 6T full CMOS SRAM cell. When the channels of all the transistors are formed in the single crystal silicon substrate, it is called a single crystalline bulk CMOS 6T SRAM cell. It is also referred to as a planar SRAM cell when all the transistors are made in the same substrate material (e.g., bulk crystalline silicon, SOI, etc.). In order to improve the stability of the cell so as to improve data retention characteristics, the widths and lengths of the p-channel (20, 22) and n-channel (16, 18, 24, 26) transistors are matched for the two inverters (12, 14).
FIGS. 1B and 1C show layout diagrams of prior SRAM cells with low aspect ratios. Aspect ratio is defined as the ratio of length to width. The bitlines (70, 72) are shown in the y-direction. The cell measurement in the direction of the bitlines defines the length of the cell and the measurements in the x-direction defines the width of the cell. A ratio of less than 2:1 is considered low aspect ratio for an SRAM cell as opposed to a ratio of about 3:1 for long aspect ratio cells. In FIGS. 1B and IC, the gates of the transistors 20-26 are formed using polysilicon lines 34 and 36 extending over p-type moat regions 42 and 44 for p-channel transistors 20 and 22 and extending over n-type moat regions 46 for the n-channel transistors 24 and 26. A transistor gate is defined as the region common to the polysilicon and moat regions of a transistor which forms the conduction channel between the source and drain when the transistor is turned on. The transistor gate for the transistors 20, 22, 24, and 26 is the common region between polysilicon line 34 and moat 42 (region 90), polysilicon line 36 and moat region 44 (region 92), polysilicon line 34 and moat region 46(region 94) and polysilicon region 36 and moat region 46 (region 96), respectively. The cross-coupling of the inverters 12 and 14 is accomplished using metal lines 38 and 40. In FIG. 1B, the gates of p-channel transistors 20 and 22 (regions 90 and 92) are vertically offset (offset in the y-direction) from gates of the n-channel transistors 24 and 26 (regions 94 and 96). The p-channel transistor gate 90 of inverter 12 is not horizontally offset (offset in the x-direction) from n-channel transistor gate 94 and p-channel transistor gate 92 is not horizontally offset from n-channel transistor gate 96. In FIG. 1C, the p-channel transistor gates 90 and 92 are also vertically offset from the n-channel transistor gates 94 and 96. In addition, p-channel transistor gate 90 is offset in a left or negative horizonal (xxe2x88x92) direction from n-channel transistor gate 94 and p-channel transistor gate 92 is offset in a right or positive horizonal (x+) direction from n-channel transistor gate 96. Thus, the p-channel transistor gates 90 and 92 are offset from their respective n-channel transistor gates 94 and 96 is opposite directions.
The p-channel transistor gates 90 and 92 are placed at equal distance from and are on opposites sides of an imaginary vertical line drawn at the middle of the two n-channel transistor gates 94 and 96. In other words, if xn1,yn1 are the x,y co-ordinates for the center point of the n-channel pull-down transistor gate 94 for inverter 12; xn2,yn2 are the x,y co-ordinates for the center point of the n-channel pull-down transistor gate 96 for inverter 14; xp1,yp1 are the x,y co-ordinates for the center point of the p-channel pull-up transistor gate 90 for inverter 12; and xp2,yp2 are the x,y co-ordinates for the center point of the p-channel pull-up transistor gate 92 for inverter 14, then the mean (xnm) of the xn1 and xn2 values is equal to the mean (xpm) of xp1 and xp2. This is true even if the gate length of the p-channel transistors 20, 22 is different than the gate length of the n-channel transistors 24, 26.
In order to minimize cell area, process design rules, such as metal overlap, are sometimes violated. For example, the metal overlap of contact design rule is violated in FIGS. 1B and 1C at regions 80, 82, and 84. This, in turn reduces the process margins. As density and performance requirements increase it becomes more and more desirable to maximize process margins while minimizing cell area.